HACK: ARM: dts: am571x-idk: Configure DSP & IVA clocks for OPP_HIGH

Commits 76715af0 ("ARM: dts: dra7xx-clocks: Set DSP DPLL and its
output clock rates") and b5783b92 ("ARM: dts: dra7xx-clocks: Set
IVA DPLL and its output clock rates") has configured the DSP and IVA
DPLL output clocks for OPP_NOM for all the DRA7 platforms, thereby
initializing the DPLL clocks and matching the default OPP_NOM voltage
setting in u-boot. Override and update these default clock rates to
OPP_HIGH values for the AM571x IDK to satisfy the performance needs
for Multimedia 1080p and various high-performance DSP usecases like
OpenCL.

The divider output rates are chosen based on the OPP_HIGH values
(700 MHz for DSP and 532 MHz for IVA) defined as per the DRA7xx PLL
spec v0.4WIPa, and match the values in the latest AM571x Data Manual.
Note that the max frequency for DSPs on AM571x is 700 MHz as compared
to 750 MHz on AM572x SoCs.

NOTE:
1. This requires that the bootloader has setup the and DSPEVE and
   IVA Voltage domains appropriately for OPP_HIGH.
2. The AM571x IDK _uses_ ganged voltage rails for DSPEVE, IVA and
   GPU voltage domains. So, the GPU clock frequency should also be
   configured properly for OPP_HIGH.

Signed-off-by: Suman Anna <s-anna@ti.com>