ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates

The IVA DPLL in DRA7xx provides the output clocks for only the IVAHD
subsystem in DRA7xx as compared to previous OMAP generations when it
provided the clocks for both DSP and IVAHD subsystems. This DPLL is
currently not configured by bootloader. Use the DT standard properties
"assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock
rate and the rates for its derivative clocks at boot time to avoid any
functional issues caused when using the IVAHD subsystem if the DPLL is
not locked. The DPLL will automatically transition into a low-power
stop mode when the associated output clocks are not utilized or gated
automatically.

The reset value of the divider M2 (that supplies the IVA_GFLCK, the
functional clock for the IVAHD subsystem) does not match a specific
OPP. So, the derived output clock from this IVA DPLL has to be
initialized as well to avoid initializing these divider outputs to an
incorrect frequencies.

The clock rates are chosen based on the OPP_NOM values defined as per the
DRA7xx PLL spec v0.4WIPa. The DPLL locked frequency is 2300 MHz, so the
dpll_iva_ck clock rate used is half of this value. The value for the
divider clock, dpll_iva_m2_ck, has to be set to 388.333334 MHz or more
for the divider clk logic to compute the appropriate divider value for
OPP_NOM.

Signed-off-by: Suman Anna <s-anna@ti.com>