drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock

The divider values in the sdcc1_apps frequency table were incorrectly
updated, assuming the frequency of gpll2_out_main to be 1152MHz.
However, the frequency of the gpll2_out_main clock is actually 576MHz
(gpll2/2).

Due to these incorrect divider values, the sdcc1_apps clock is running
at half of the expected frequency.

Fixing the frequency table of sdcc1_apps allows the sdcc1_apps clock to
run according to the frequency plan.

Fixes: 21b5d5a4 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC")
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250306112900.3319330-1-quic_mmanikan@quicinc.com


Signed-off-by: Bjorn Andersson <andersson@kernel.org>