Commit c567bc5f authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Drew Fustini
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clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL



The AXI crossbar of TH1520 has no proper timeout handling, which means
gating AXI clocks can easily lead to bus timeout and thus system hang.

Set all AXI clock gates to CLK_IS_CRITICAL. All these clock gates are
ungated by default on system reset.

In addition, convert all current CLK_IGNORE_UNUSED usage to
CLK_IS_CRITICAL to prevent unwanted clock gating.

Signed-off-by: default avatarIcenowy Zheng <uwu@icenowy.me>
Reviewed-by: default avatarDrew Fustini <fustini@kernel.org>
Signed-off-by: default avatarDrew Fustini <fustini@kernel.org>
parent 8fede7ff
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