lrdp_v2 : Fix for broken clockdump.py

clockdump.py is taking more time because it is going thourgh all
node of of_clk_provider, and some of the node does not have any data
so need to skip those node and continue.
parsing new clk 'spmi_pmic_div_clk_hw_get' added in kernel 4.14

Change-Id: Iaccb93baa566eaaf3031cd7ec2d112f8c867cd38

linux-ramdump-parser-v2/parsers/clockdump.py

@@ -29,7 +29,7 @@ class ClockDumps(RamParser):
             self.output_file.write("--------------------------------------------\n")
             self.output_file.write("{0} from of_clk_providers list\n".format(title))
             self.output_file.write("--------------------------------------------\n")
-            str = "  {0:40} {1:21} {2:25} {3:20} {4:45} {5:40}\n"
+            str = "  {0:40} {1:21} {2:25} {3:10} {4:45} {5:40}\n"
             self.output_file.write(str.format('CLOCK NAME',
                                             'COUNT/PREPARE_COUNT',
                                             'RATE', 'CUR_LEVEL',
@@ -170,17 +170,16 @@ class ClockDumps(RamParser):
                                 clk_core, 'struct clk_core', 'enable_count')
         clk_rate = self.ramdump.read_structure_field(
                                     clk_core, 'struct clk_core', 'rate')
-        clk_vdd_class_addr = self.ramdump.read_structure_field(
+        vdd_class = self.ramdump.read_structure_field(
                                 clk_core,'struct clk_core','vdd_class')
         clk_ops = self.ramdump.read_structure_field(
                                 clk_core,'struct clk_core','ops')
         clk_ops = self.ramdump.unwind_lookup(clk_ops)
-        vdd_class = self.ramdump.read_word(clk_vdd_class_addr)
         cur_level = 0
         if vdd_class != 0 and vdd_class is not None:
             cur_level_address = (vdd_class + offset_vdd_cur_level)
             cur_level = self.ramdump.read_word(cur_level_address, True)
-        formatStr = "{0:40} {1:<2}/ {2:<17} {3:<25} {4:<20} " \
+        formatStr = "{0:40} {1:<2}/ {2:<17} {3:<25} {4:<10} " \
                     "v.v (struct clk_core *)0x{5:<20x} {6:<40}\n"
         output = formatStr.format(
                                 clk_name,
@@ -230,35 +229,57 @@ class ClockDumps(RamParser):
             self.dump_clock(clk_core,clk_name)
             counter = counter + 1
 
-    def print_clk_qcom_cc_data(self, data, node):
-        getfunchw = self.ramdump.read_structure_field(
-                            node,'struct of_clk_provider','get_hw')
-        getfunchw = self.ramdump.unwind_lookup(getfunchw)
-
-        if "qcom_cc_clk_hw_get" in getfunchw:
-            size = self.ramdump.read_structure_field(
-                            data,'struct qcom_cc','num_rclks')
-            clks = self.ramdump.read_structure_field(
-                            data,'struct qcom_cc','rclks')
-            sizeof_clk_regmap = self.ramdump.sizeof('struct clk_regmap *')
-            offset_vdd_cur_level = self.ramdump.field_offset(
-                'struct clk_vdd_class', 'cur_level')
-            counter = 0
-            while counter < size:
-                clk = self.ramdump.read_word(clks +
-                                             (sizeof_clk_regmap * counter))
-                clk_core = self.ramdump.read_structure_field(
-                                    clk,'struct clk_regmap','hw.core')
-                if clk_core == 0 or clk_core is None:
-                    counter = counter + 1
-                    continue
-                clk_name_addr = self.ramdump.read_structure_field(
-                                    clk_core, 'struct clk_core', 'name')
-                clk_name = self.ramdump.read_cstring(clk_name_addr, 48)
-                if (clk_name == 0 or clk_name == None):
-                    break
-                self.dump_clock(clk_core,clk_name)
+    # qcom_cc_clk_hw_get clk is added in kernel 4.9
+    def print_clk_qcom_cc_data(self, data):
+        size = self.ramdump.read_structure_field(
+                        data,'struct qcom_cc','num_rclks')
+        clks = self.ramdump.read_structure_field(
+                        data,'struct qcom_cc','rclks')
+        sizeof_clk_regmap = self.ramdump.sizeof('struct clk_regmap *')
+        offset_vdd_cur_level = self.ramdump.field_offset(
+                        'struct clk_vdd_class', 'cur_level')
+        counter = 0
+        while counter < size:
+            clk = self.ramdump.read_word(clks +
+                                 (sizeof_clk_regmap * counter))
+            clk_core = self.ramdump.read_structure_field(
+                                clk,'struct clk_regmap','hw.core')
+            if clk_core == 0 or clk_core is None:
                 counter = counter + 1
+                continue
+            clk_name_addr = self.ramdump.read_structure_field(
+                                clk_core, 'struct clk_core', 'name')
+            clk_name = self.ramdump.read_cstring(clk_name_addr, 48)
+            if (clk_name == 0 or clk_name == None):
+                break
+            self.dump_clock(clk_core,clk_name)
+            counter = counter + 1
+
+    # spmi_pmic_div_clk_hw_get clk is added kernel 4.14
+    def print_clk_spmi_pmic_data(self, data):
+        size = self.ramdump.read_structure_field(
+                        data,'struct spmi_pmic_div_clk_cc','nclks')
+        clks = self.ramdump.field_offset(
+                        'struct spmi_pmic_div_clk_cc','clks')
+        clks = data + clks
+        sizeof_clk_regmap = self.ramdump.sizeof('struct clkdiv')
+        offset_vdd_cur_level = self.ramdump.field_offset(
+                    'struct clk_vdd_class', 'cur_level')
+        counter = 0
+        while counter < size:
+            clk = clks + (sizeof_clk_regmap * counter)
+            clk_core = self.ramdump.read_structure_field(
+                                clk,'struct clkdiv','hw.core')
+            if clk_core == 0 or clk_core is None:
+                counter = counter + 1
+                continue
+            clk_name_addr = self.ramdump.read_structure_field(
+                                clk_core, 'struct clk_core', 'name')
+            clk_name = self.ramdump.read_cstring(clk_name_addr, 48)
+            if (clk_name == 0 or clk_name == None):
+                break
+            self.dump_clock(clk_core,clk_name)
+            counter = counter + 1
 
     def clk_providers_walker(self, node):
         if node == self.head:
@@ -267,15 +288,27 @@ class ClockDumps(RamParser):
                                     'struct of_clk_provider', 'data')
         data = self.ramdump.read_word(data_address, True)
 
+        getfunc = self.ramdump.read_structure_field(
+                        node,'struct of_clk_provider','get')
+        if getfunc == 0:
+            getfunchw = self.ramdump.read_structure_field(
+                            node,'struct of_clk_provider','get_hw')
+            getfunchw = self.ramdump.unwind_lookup(getfunchw)
+            if "spmi_pmic_div_clk_hw_get" in getfunchw:
+                self.print_clk_spmi_pmic_data(data)
+                return
+            elif "qcom_cc_clk_hw_get" in getfunchw:
+                self.print_clk_qcom_cc_data(data)
+                return
+            else:
+                return
+
         if (self.ramdump.is_config_defined('CONFIG_COMMON_CLK_MSM')):
             self.print_clk_of_msm_provider_data(data)
         else:
             self.print_clk_onecell_data(data)
 
-        getfunc = self.ramdump.read_structure_field(
-                        node,'struct of_clk_provider','get')
-        if getfunc == 0:
-            self.print_clk_qcom_cc_data(data,node)
+
 
     def parse(self):
         self.output_file = self.ramdump.open_file('ClockDumps.txt')