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Commit 424a03e4 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "lrdp_v2 : Fix for broken clockdump.py"

parents c6301841 8207be4d
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linux-ramdump-parser-v2/parsers/clockdump.py
+ 69
− 36
View file @ 424a03e4
...@@ -29,7 +29,7 @@ class ClockDumps(RamParser): ...@@ -29,7 +29,7 @@ class ClockDumps(RamParser):
self.output_file.write("--------------------------------------------\n") self.output_file.write("--------------------------------------------\n")
self.output_file.write("{0} from of_clk_providers list\n".format(title)) self.output_file.write("{0} from of_clk_providers list\n".format(title))
self.output_file.write("--------------------------------------------\n") self.output_file.write("--------------------------------------------\n")
str = " {0:40} {1:21} {2:25} {3:20} {4:45} {5:40}\n" str = " {0:40} {1:21} {2:25} {3:10} {4:45} {5:40}\n"
self.output_file.write(str.format('CLOCK NAME', self.output_file.write(str.format('CLOCK NAME',
'COUNT/PREPARE_COUNT', 'COUNT/PREPARE_COUNT',
'RATE', 'CUR_LEVEL', 'RATE', 'CUR_LEVEL',
...@@ -170,17 +170,16 @@ class ClockDumps(RamParser): ...@@ -170,17 +170,16 @@ class ClockDumps(RamParser):
clk_core, 'struct clk_core', 'enable_count') clk_core, 'struct clk_core', 'enable_count')
clk_rate = self.ramdump.read_structure_field( clk_rate = self.ramdump.read_structure_field(
clk_core, 'struct clk_core', 'rate') clk_core, 'struct clk_core', 'rate')
clk_vdd_class_addr = self.ramdump.read_structure_field( vdd_class = self.ramdump.read_structure_field(
clk_core,'struct clk_core','vdd_class') clk_core,'struct clk_core','vdd_class')
clk_ops = self.ramdump.read_structure_field( clk_ops = self.ramdump.read_structure_field(
clk_core,'struct clk_core','ops') clk_core,'struct clk_core','ops')
clk_ops = self.ramdump.unwind_lookup(clk_ops) clk_ops = self.ramdump.unwind_lookup(clk_ops)
vdd_class = self.ramdump.read_word(clk_vdd_class_addr)
cur_level = 0 cur_level = 0
if vdd_class != 0 and vdd_class is not None: if vdd_class != 0 and vdd_class is not None:
cur_level_address = (vdd_class + offset_vdd_cur_level) cur_level_address = (vdd_class + offset_vdd_cur_level)
cur_level = self.ramdump.read_word(cur_level_address, True) cur_level = self.ramdump.read_word(cur_level_address, True)
formatStr = "{0:40} {1:<2}/ {2:<17} {3:<25} {4:<20} " \ formatStr = "{0:40} {1:<2}/ {2:<17} {3:<25} {4:<10} " \
"v.v (struct clk_core *)0x{5:<20x} {6:<40}\n" "v.v (struct clk_core *)0x{5:<20x} {6:<40}\n"
output = formatStr.format( output = formatStr.format(
clk_name, clk_name,
...@@ -230,35 +229,57 @@ class ClockDumps(RamParser): ...@@ -230,35 +229,57 @@ class ClockDumps(RamParser):
self.dump_clock(clk_core,clk_name) self.dump_clock(clk_core,clk_name)
counter = counter + 1 counter = counter + 1
def print_clk_qcom_cc_data(self, data, node): # qcom_cc_clk_hw_get clk is added in kernel 4.9
getfunchw = self.ramdump.read_structure_field( def print_clk_qcom_cc_data(self, data):
node,'struct of_clk_provider','get_hw') size = self.ramdump.read_structure_field(
getfunchw = self.ramdump.unwind_lookup(getfunchw) data,'struct qcom_cc','num_rclks')
clks = self.ramdump.read_structure_field(
if "qcom_cc_clk_hw_get" in getfunchw: data,'struct qcom_cc','rclks')
size = self.ramdump.read_structure_field( sizeof_clk_regmap = self.ramdump.sizeof('struct clk_regmap *')
data,'struct qcom_cc','num_rclks') offset_vdd_cur_level = self.ramdump.field_offset(
clks = self.ramdump.read_structure_field( 'struct clk_vdd_class', 'cur_level')
data,'struct qcom_cc','rclks') counter = 0
sizeof_clk_regmap = self.ramdump.sizeof('struct clk_regmap *') while counter < size:
offset_vdd_cur_level = self.ramdump.field_offset( clk = self.ramdump.read_word(clks +
'struct clk_vdd_class', 'cur_level') (sizeof_clk_regmap * counter))
counter = 0 clk_core = self.ramdump.read_structure_field(
while counter < size: clk,'struct clk_regmap','hw.core')
clk = self.ramdump.read_word(clks + if clk_core == 0 or clk_core is None:
(sizeof_clk_regmap * counter))
clk_core = self.ramdump.read_structure_field(
clk,'struct clk_regmap','hw.core')
if clk_core == 0 or clk_core is None:
counter = counter + 1
continue
clk_name_addr = self.ramdump.read_structure_field(
clk_core, 'struct clk_core', 'name')
clk_name = self.ramdump.read_cstring(clk_name_addr, 48)
if (clk_name == 0 or clk_name == None):
break
self.dump_clock(clk_core,clk_name)
counter = counter + 1 counter = counter + 1
continue
clk_name_addr = self.ramdump.read_structure_field(
clk_core, 'struct clk_core', 'name')
clk_name = self.ramdump.read_cstring(clk_name_addr, 48)
if (clk_name == 0 or clk_name == None):
break
self.dump_clock(clk_core,clk_name)
counter = counter + 1
# spmi_pmic_div_clk_hw_get clk is added kernel 4.14
def print_clk_spmi_pmic_data(self, data):
size = self.ramdump.read_structure_field(
data,'struct spmi_pmic_div_clk_cc','nclks')
clks = self.ramdump.field_offset(
'struct spmi_pmic_div_clk_cc','clks')
clks = data + clks
sizeof_clk_regmap = self.ramdump.sizeof('struct clkdiv')
offset_vdd_cur_level = self.ramdump.field_offset(
'struct clk_vdd_class', 'cur_level')
counter = 0
while counter < size:
clk = clks + (sizeof_clk_regmap * counter)
clk_core = self.ramdump.read_structure_field(
clk,'struct clkdiv','hw.core')
if clk_core == 0 or clk_core is None:
counter = counter + 1
continue
clk_name_addr = self.ramdump.read_structure_field(
clk_core, 'struct clk_core', 'name')
clk_name = self.ramdump.read_cstring(clk_name_addr, 48)
if (clk_name == 0 or clk_name == None):
break
self.dump_clock(clk_core,clk_name)
counter = counter + 1
def clk_providers_walker(self, node): def clk_providers_walker(self, node):
if node == self.head: if node == self.head:
...@@ -267,15 +288,27 @@ class ClockDumps(RamParser): ...@@ -267,15 +288,27 @@ class ClockDumps(RamParser):
'struct of_clk_provider', 'data') 'struct of_clk_provider', 'data')
data = self.ramdump.read_word(data_address, True) data = self.ramdump.read_word(data_address, True)
getfunc = self.ramdump.read_structure_field(
node,'struct of_clk_provider','get')
if getfunc == 0:
getfunchw = self.ramdump.read_structure_field(
node,'struct of_clk_provider','get_hw')
getfunchw = self.ramdump.unwind_lookup(getfunchw)
if "spmi_pmic_div_clk_hw_get" in getfunchw:
self.print_clk_spmi_pmic_data(data)
return
elif "qcom_cc_clk_hw_get" in getfunchw:
self.print_clk_qcom_cc_data(data)
return
else:
return
if (self.ramdump.is_config_defined('CONFIG_COMMON_CLK_MSM')): if (self.ramdump.is_config_defined('CONFIG_COMMON_CLK_MSM')):
self.print_clk_of_msm_provider_data(data) self.print_clk_of_msm_provider_data(data)
else: else:
self.print_clk_onecell_data(data) self.print_clk_onecell_data(data)
getfunc = self.ramdump.read_structure_field(
node,'struct of_clk_provider','get')
if getfunc == 0:
self.print_clk_qcom_cc_data(data,node)
def parse(self): def parse(self):
self.output_file = self.ramdump.open_file('ClockDumps.txt') self.output_file = self.ramdump.open_file('ClockDumps.txt')
......
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