msm: acpuclock-7201: Add acpu freq. tables for PLL1 at 737/589 MHz

PLL1 output frequency is now changed to 737.28MHz and 589.824MHz
for GSM and CDMA configuration resp. to achieve the 33% duty
cycle for adsp.

Add the required acpu frequency tables to reflect the same.

Tables for 245/196 PLL1 freq. are still kept to keep the backward
compatibility.

CRs-Fixed: 319835
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
(cherry picked from commit 9bb022c2)

Change-Id: I404780b4174573344d09b8f1d76657830bf73270
Signed-off-by: Srivalli Oguri <oguri@codeaurora.org>