arm64: dts: qcom: x1e80100: Describe the SDHC controllers

The X Elite platform features two SDHC v5 controllers.

Describe the controllers along with the pin configuration in TLMM
for the SDC2, since they are hardwired and cannot be muxed to any
other function. The SDC4 pin configuration can be muxed to different
functions, so leave those to board specific dts.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241212-x1e80100-qcp-sdhc-v4-1-a74c48ee68a3@linaro.org


[bjorn: Replaced 0s with QCOM_ICC_TAG_ALWAYS]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>