Commit f95dbe82 authored by Roger Quadros's avatar Roger Quadros Committed by Vignesh Raghavendra
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net: ethernet: ti: icssg_prueth: add periodic output support 



Firmware can't deal with period of less than cycle time (1 ms).
Firmware takes care of setting the SYNC_EN pulse every cycle.

If the period is greater than firmware cycle time (1ms) then
we need to set number of cycles in
TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET and remaining
time in CMP register.

Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
parent aa1958b6
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