Commit f5d07956 authored by Jessica Zhang's avatar Jessica Zhang Committed by Dmitry Baryshkov
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drm/msm/dpu: Fix adjusted mode clock check for 3d merge



Since 3D merge allows for larger modes to be supported across 2 layer
mixers, filter modes based on adjusted mode clock / 2 when 3d merge is
supported.

Reported-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Fixes: 62b7d683 ("drm/msm/dpu: Filter modes based on adjusted mode clock")
Signed-off-by: default avatarJessica Zhang <jessica.zhang@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Tested-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Tested-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/676353/
Link: https://lore.kernel.org/r/20250923-modeclk-fix-v2-1-01fcd0b2465a@oss.qualcomm.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent bbc65d1b
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