Commit e1a09833 authored by John Madieu's avatar John Madieu Committed by Geert Uytterhoeven
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clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP 



Add required clocks and resets signals for the TSU IP available on the
Renesas RZ/G3E SoC

Signed-off-by: default avatarJohn Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250227122453.30480-3-john.madieu.xa@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 69ac2acd
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