clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks

On Amlogic SoCs, the rate of a peripheral clock should not be changed,
let alone the rate of the parent PLL.

These clocks are meant to be used as provided by the parent PLL. Changing
the rate would be dangerous and would likely break a lot of devices running
from the same PLL.

Don't propagate any rate change request that may come from these clocks and
drop the corresponding flag.

Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-6-0f402f01e117@baylibre.com


Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>