UPSTREAM: drm/i915: Keep TRANS_VBLANK.vblank_start==0 on ADL+ even when doing LRR updates

intel_set_transcoder_timings() will set TRANS_VBLANK.vblank_start to 0
for clarity on ADL+ (non-DSI) because the hardware no longer uses that
value. Do the same in intel_set_transcoder_timings_lrr() to make sure
the registers stay consistent even when doing LRR timing updates.

Cc: Paz Zcharya <pazz@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250116201637.22486-2-ville.syrjala@linux.intel.com


Reviewed-by: Jani Nikula <jani.nikula@intel.com>
(cherry picked from commit c5303240)

Bug: 432032023
Test: None
Change-Id: Ibe9cd0efdfaa687a7b8979829777f421b19d4471
Signed-off-by: Ap, Kamal <kamal.ap@intel.corp-partner.google.com>