clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining SCIFs

The Renesas RZ/G3S SoC has 6 SCIF interfaces.  SCIF0 is used as debug
console and is already enabled.  Add clock, reset and power domain
support for the remaining ones.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241115134401.3893008-2-claudiu.beznea.uj@bp.renesas.com


Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>