riscv: traps_misaligned: properly sign extend value in misaligned load handler

Add missing cast to signed long.

Signed-off-by: Andreas Schwab <schwab@suse.de>
Fixes: 956d705d ("riscv: Unaligned load/store handling for M_MODE")
Tested-by: Clément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de


Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>