ANDROID: arm64: dma: Panic if ARCH_DMA_MINALIGN is less than CTR_EL0.CWG

If the value of ARCH_DMA_MINALIGN is less than the cache line size of
the system, it is not possible to safely perform non-coherent DMA
transactions. For example, if a DMA buffer is used for non-coherent
DMA from a device, and that buffer shares a cacheline with another
buffer that the CPU operated on in the past, the data from the device
will be overwritten if the cacheline is evicted.

These sort of DMA corruptions are non-trivial to find, so instead of
allowing a system to continue booting and potentially initiate an
unsafe DMA transaction, trigger a kernel panic if the minimum DMA
alignment is smaller than the cache line size of the system.

Bug: 241844128
Bug: 267786731
Change-Id: I97998a4b3eea25d0956416c020ac0a6aa6950fb8
Signed-off-by: Isaac J. Manjarres <isaacmanjarres@google.com>