UPSTREAM: drm/i915/dp_mst: Account for channel coding efficiency in the DSC DPT bpp limit

The DSC DPT interface BW limit check should take into account the link
clock's (aka DDI clock in bspec) channel coding efficiency overhead.
Bspec suggests that the FEC overhead needs to be applied, however HW
people claim this isn't the case, nor is any overhead applicable.

However based on testing various 5k/6k modes both on the DELL U3224KBA
monitor and the Unigraf UCD-500 CTS test device, both the channel coding
efficiency (which includes the FEC overhead) and an additional 3%
overhead must be accounted for to get these modes working.

Bspec: 49259

v2:
- Apply an additional 3% overhead, add a commit log and code comment
  about these overheads and the relation to the Bspec BW limit formula.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240416221010.376865-5-imre.deak@intel.com


(cherry picked from commit fd13841d)

BUG=b:332903004, b:322223603
TEST=Verify Dell U3224KB 6k mode on Rex using UHBR, MST encoder, Big
     Joiner, and DSC

Change-Id: I12097329b1921d645d074dd55efe516fa22c1315
Signed-off-by: Rakshith M O <rakshith.m.o@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/5802885


Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Reviewed-by: Sean Paul <sean@poorly.run>
Signed-off-by: Hubert Mazur <hmazur@google.com>