Unverified Commit 9e6b8155 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'riscv-cache-for-v6.11' of...

Merge tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into soc/drivers

RISC-V cache drivers for v6.11

StarFive:
A new driver for the cache controller on the jh8100, which didn't
implement Zicbom and thus needs an implementation of non-standard cache
management operations.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  MAINTAINERS: add microchip soc binding directory to microchip soc driver entry
  MAINTAINERS: add cache binding directory to cache driver entry
  cache: Add StarFive StarLink cache management
  dt-bindings: cache: Add docs for StarFive Starlink cache controller

Link: https://lore.kernel.org/r/20240707-whoever-undesired-c5f6e96ae403@spud


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a4dd55f8 3d41249c
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