Commit 989d673f authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI 



Add clock and reset entries for the DRP-AI block, which is available only
on the Renesas RZ/V2L SoC.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250106202853.262787-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 5599c7c4
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