i2c: exynos5: Calculate t_scl_l, t_scl_h according to i2c spec

Previously the duty cycle was divided equally into h_scl_l, t_scl_h.
This makes the low period of the SCL clock in Fast Mode is only 1.25us
which is way lower than the minimal value (1.3) specified in i2c
specification. In order to make sure t_scl_l, t_scl_h always fullfill
i2c specification, this commit calculates t_scl_l using this formula:

t_scl_l = clk_cycle *
    ((t_low_min + (scl_clock - t_low_min - t_high_min) / 2) / scl_clock)

where:
t_low_min is the minimal value of low period of the SCL clock in us;
t_high_min is the minimal value of high period of the SCL clock in us;
scl_clock is converted from SCL clock frequency into us.

Signed-off-by: Camel Guo <camel.guo@axis.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>