Commit 831a8ac7 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Heiko Stuebner
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clk: rockchip: rk3588: Add PLL rate for 1500 MHz 



At least one RK3588 clock (CPLL) uses 1.5 GHz, so let's add
that frequency to the PLL table.

Signed-off-by: default avatarAlexander Shiyan <eagle.alexander923@gmail.com>
Link: https://lore.kernel.org/r/20250408064612.41359-1-eagle.alexander923@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 0af2f6be
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