ARM: DRA7: hwmod data: Add MMU data for IPUs & DSP1

A new MMU hwmod class and data structures are added for representing
the MMUs within the IPU and DSP processor subsystems present in
DRA7xx SoCs. The DRA7xx family of SoCs usually have two IPUs with an
MMU each, and a DSP with two MMUs, one for the processor core and the
other for the internal EDMA block.

NOTE:
1. The functional clocks for IPU1 and IPU2 are slightly different.
   IPU2 functional clock is sourced directly from dpll_core_h22x2_ck,
   while IPU1 has a mux clock for which one of the inputs is
   dpll_core_h22x2_ck. This mux clock is expected to be configured
   to be sourced from the dpll_core_h22x2_ck in turn, so that both
   IPU1 and IPU2 run at the same clock frequency.
2. The DSP processor subsystem in DRA7xx has two MMUs, one for the
   processor port and another for an EDMA port. Both these MMUs
   share a common reset line, the MMU on the EDMA port is expected
   to be mirror-programmed alongside the primary MMU, with the reset
   handled by the OMAP IOMMU driver. The reset data is added to both
   the MMUs to allow the omap_hwmod layer to skip the enabling and
   idling of these devices, as that would require the reset be
   released, which is outside the scope of the hwmod core code. The
   pdata quirks will not be added though for the second MMU as the
   OMAP IOMMU driver releases the reset once and programs both the
   MMUs together.

Signed-off-by: Suman Anna <s-anna@ti.com>