clk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLs
Add clock ops for Taycan PLL, add the register offsets for supporting the PLL. Signed-off-by:Melody Olvera <quic_molvera@quicinc.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-4-1a8f31a53a86@quicinc.com Signed-off-by:
Bjorn Andersson <andersson@kernel.org>
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