Commit 5db13ece authored by Duy Nguyen's avatar Duy Nguyen Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores 



Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4M (R8A779H0) SoC, including CPU
topology and PSCI support for enabling CPU cores.

Signed-off-by: default avatarDuy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c2a38a0da74915bf2a9171e53886c83a1c732934.1706796979.git.geert+renesas@glider.be
parent 20a942d6
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