mtd: spi-nor: cadence-quadspi: Add PHY calibration sequence for DDR mode

Update calibration sequence for Octal DDR mode. Sequence involves 2D
search to find range of TX DLL delay values and RX DLL delay values for
which controller is able to read data consistently from flash. Use
standard SFDP table as reference data to verify that reads are
consistent during 2D search.
Once ranges are obtained, choose the middle of TX and RX DLL delay
ranges as the working configuration.

Use PHY and DDR mode only for reading data from OSPI as advantage of
DDR mode for write is limited.

As per TRM, when operating in Octal DDR PHY pipeline mode, reads should
be 16 byte aligned. Use bounce buffer for unaligned reads.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>