iommu/omap: fix range for cache flush operations

Some of the pgd and pte entries are not getting flushed
completely due to incorrect ranges of the addresses passed
into the cache flush operations. This resulted in infrequent
random MMU faults on the DSP & IPU remote processors on OMAP4.

The end values used at present sufficed with the previous
usage of the assembly instructions within the page table
cache flush operations, but need to be updated to work
properly after the switch to the dmac_flush_range() and
outer_flush_range() API. So, fix the same by using the
actual end address (an additional word adjustment).

Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com>
[s-anna@ti.com: rewrite commit description]
Signed-off-by: Suman Anna <s-anna@ti.com>