Commit 3dc73106 authored by Varshini Rajendran's avatar Varshini Rajendran Committed by Claudiu Beznea
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dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT 



Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
clock from phandle in DT for sam9x7 SoC family.

Signed-off-by: default avatarVarshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20240729070803.1990916-1-varshini.rajendran@microchip.com


Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@tuxon.dev>
parent 5bf194ad
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