Commit 3bbdf8c3 authored by Duy Nguyen's avatar Duy Nguyen Committed by Geert Uytterhoeven
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dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions 



Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V4M (R8A779H0) SoC.

Signed-off-by: default avatarDuy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: default avatarHai Pham <hai.pham.ud@renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be
parent 2a899847
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