Commit 36d46e21 authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Greg Kroah-Hartman
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ASoC: fsl_asrc: refine the check of available clock divider



[ Upstream commit 32038634 ]

According to RM, the clock divider range is from 1 to 8, clock
prescaling ratio may be any power of 2 from 1 to 128.
So the supported divider is not all the value between
1 and 1024, just limited value in that range.

Create table for the supported divder and add function to
check the clock divider is available by comparing with
the table.

Fixes: d0250cf4 ("ASoC: fsl_asrc: Add an option to select internal ratio mode")
Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1641380883-20709-1-git-send-email-shengjiu.wang@nxp.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 5a6864e2
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