phy: cadence: cadence-sierra: Don't configure if any plls are already locked

Serdes lanes might be shared between multiple cores in some usecases
and its not possible to lock PLLs for both the lanes independently
by the two cores. This requires a bootloader to configure both the
lanes at early boot time.

To handle this case, skip all configuration if any of the plls are
already locked. This is done by adding an already_configured flag
and using it to gate every register access as well as any phy_ops.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>