Commit 2eb68366 authored by Pritesh Patel's avatar Pritesh Patel Committed by Conor Dooley
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dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility



This cache controller is also used on the ESWIN EIC7700 SoC.
However, it have 256KB private L2 Cache and shared L3 Cache of 4MB.
So add dedicated compatible string for it.

Signed-off-by: default avatarPritesh Patel <pritesh.patel@einfochips.com>
Reviewed-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Signed-off-by: default avatarPinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 0af2f6be
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