Commit 20a942d6 authored by Duy Nguyen's avatar Duy Nguyen Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a779h0: Add L3 cache controller 



Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: default avatarDuy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/9d56a46892c5e0957d244370e6809013cf815905.1706796979.git.geert+renesas@glider.be
parent 93e28f88
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