Commit 09631115 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a779g0: Fix PCIe clock name



Fix a typo in the name of the module clock for the second PCIe channel.

Fixes: 5ab16198 ("clk: renesas: r8a779g0: Add PCIe clocks")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f582067564f357e2183d3db67b217084ecb51888.1706608032.git.geert+renesas@glider.be
parent f077cab3
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