Commit f11928ab authored by Matt Wagantall's avatar Matt Wagantall Committed by QuIC Gerrit Code Review
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msm: pil-q6v5-mss: Add memory barrier after RMB_MBA_IMAGE write 



Ensure the write of the image address in the RMB_MBA_IMAGE RMB
register occurs before the writes to the QDSP6SS that releases
the Q6 processor from reset.

Change-Id: I7efbe4e0b81153cc2dc15d8ec60173008478b826
Signed-off-by: default avatarMatt Wagantall <mattw@codeaurora.org>
parent 29f4b0c2
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