Commit eb78cbf1 authored by Niranjana Vishwanathapura's avatar Niranjana Vishwanathapura
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msm: pcie: Disable secondary bus reset functionality 



Setting the 'Secondary Bus Reset' bit in 'Bridge Control' register
of root complex port configuration space is causing the PCIE core to
reset due to hardware limitation. Discard any request to set this bit.

Change-Id: Iacad6ba8e8a49406428bf875901817f3f96fa24d
Signed-off-by: default avatarNiranjana Vishwanathapura <nvishwan@codeaurora.org>
parent 0afb2516
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