INTERNAL: arm64: dts: qcom: qcs404: Add USB devices and PHYs

QCS404 sports HS and SS USB controllers based on dwc3 block with two HS
PHYs and one SS PHY. Add nodes for these devices and enable them for
EVB board.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@linaro.org>

arm64: dts: qcom: qcs404: Describe USB3 reset

In the scenario where the bootloader doesn't deassert the USB3 reset,
the kernel will fail to enable USB3 master clock. This results in the
clock code spitting out a warning about the clock being stuck, with
the "clock enable lock" held and interrupts disabled.

As the warning is transmitted to the UART, there's a significant delay
(~300ms), during which interrupt handlers are prevented from executing.

A result of this is seen as SPI transfers during boot being timed out,
because the interrupt handler is prevented from running to indicate the
transfer as complete.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@linaro.org>