Commit b76f190d authored by Matt Wagantall's avatar Matt Wagantall
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msm: pil-q6v5: Disable Q6 core_clk and core_rclk gating 



Leaving clock gating enabled for these causes issues for
JTAG debugging. Disable clock gating by default and leave
enabling it again to the Q6 software.

Change-Id: Id6c41b93b94e5fe05a80918aa1e0ce129e857ccc
Signed-off-by: default avatarMatt Wagantall <mattw@codeaurora.org>
parent 3e041840
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