msm: clock-8960: Support alternate PLL4 clock plan

PLL4 may be running at either 491.52MHz or 393.216MHz. Detect the
rate at runtime and select the appropriate frequency tables so that
the same rates for PLL4-based clocks can be used with either
configuration.

To ensure that any PLL configuration done as part of reg_init()
takes place before the rate-detection occurs, move the reg_init()
call to the top of msm8960_clock_pre_init().

Change-Id: I547ce16334acaeee4797147e47684672d8a5bade
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>