msm: acpuclock-krait: Enforce CPU HFPLL vdd_dig requirements

Part of the CPU HFPLL logic lives in the vdd_dig domain and has
voltage requirements that vary based on the PLL frequency. Capture
this in the code.

Even without this change, vdd_dig levels are sufficiently high due
to the vdd_dig votes already made for the L2. This change improves
robustness, however, and protects us should the CPU->L2 frequency
mappings ever change.

Change-Id: Id54a97a5be5dbe4ba61d6fa8ba5b259b3538a0be
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>