msm: pil-q6v5: Enable subsystem's bus_clk before calling clk_reset()

For MSS, the gcc_mss_cfg_ahb clock must be enabled for clk_reset(core_clk)
to succeed, since the reset operations requires access to clock
controller registers that are only accessible when that clock is on.

Change the order of calls in pil_q6v5_enable_clks() and in
pil_q6v5_disable_clks() so that this constraint is obeyed.

Change-Id: I43d19de36608601d8bd0b3d8f042023f9b2eb9ba
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>