Commit 4ddc453f authored by Anji jonnala's avatar Anji jonnala
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ARM: mm: add dmb in l2xo_resume 



Add dmb after l2xo_inv_all to make sure that l2xo is invalidated
before enabling the cache.

Change-Id: Ic45bd6fd20963ac9e596a58fdd357cedf1dd2aad
Signed-off-by: default avatarAnji jonnala <anjir@codeaurora.org>
parent 7d61e0bd
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