msm: pil-pronto: Add delay after de-assertion of CLK_CTL_WCNSS_RESTART_BIT

A previous change introduced a udelay after de-asserting this
bit in another place in this driver, but this second de-assertion
was missed. Add it for similar reasons: the subsystem cannot be
accessed until the reset de-assertion has finished propagating.

Change-Id: I97abe8b81cd599ab3187f989429501d35f50aec6
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>