drm/msm/dsi: Revert to old way of saving PLL postdiv/mux regsiter state

The DSI PLL postdivider and mux states were saved and restored because
the PLL registers lost context when DSI PHY was disabled. This led to
situations where the clock framework wasn't aware about the loss of
state and wrongly calculated rates.

This was partially fixed by maintaining state in the prepare_enable/
disable clk ops of the VCO. This resolves the issue seen when
successive suspend/resumes occure without change in the display mode.

We, however, still see issues when switching between modes. In particular,
when switching between modes which have different configuratons of the
VREG_CFG mux. When setting clock rates after the previous PHY disable, the
old state isn't restored and the clock framework determines wrong rates,
and hence doesn't configure the mux and postdividers as needed by the new
rates.

We now restore the state much earlier than the VCO's prepare_enable op, so
that the we determine the new rates correctly. The state is restored/saved
in the DSI phy_enable/disable funcs, as it was done before in an older
revision of the DSI PHY patchset.

Signed-off-by: Archit Taneja <architt@codeaurora.org>