mmc: msm_sdcc: fix the clock selection logic in DDR mode

MSM SDCC controller requires the internal clock frequency to set be
doubled when running in DDR (Dual Data Rate) mode and existing
clock selection logic used to work fine until the MMC clock scaling
functionality got added. With clock scaling now, clock (ios->clock)
might get scaled down from 50MHz to 25MHz during DDR mode operation
and existing clock frequency selection logic may not change the clock
frequency when we move back from 25MHz to 50MHz.

This patch fixes the above issue and also simplifies the clock frequency
selection logic in DDR mode.

CRs-Fixed: 458926
Change-Id: I60f9ae2d5a7f92031fb46d9b16676c74363e7b9f
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>