Commit 0bb4ede2 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla
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FROMLIST: misc: fastrpc: make sure memory read and writes are visible



dma_alloc_coherent buffers could have writes queued in store buffers so
commit them before sending buffer to DSP using correct dma barriers.
Same with vice-versa.

Fixes: c68cfb71 ("misc: fastrpc: Add support for context Invoke method")
Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
parent fcc1d014
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