clk: msm: clock-cpu-8996: Increase CBF PLL post-divider to 4 for 8996pro

To open up the frequency range from 150 to 300MHz, change
the fixed CBF PLL post divider from 2 to 4. That way, to
generate frequencies less than 300MHz, the VCO can be run
at 4x with the CBF mux set to use the main output.

While we're here, add the cbf_pll_main clock to the lookup
table.

CRs-Fixed: 980903
Change-Id: I9f70f18e01199c41e1940857afb7bdd477c1c04c
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>