Commit 06cc95a1 authored by Stepan Moskovchenko's avatar Stepan Moskovchenko Committed by Dhivya Subramanian
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msm: cache_erp: Handle recoverable L1 errors 



Some CPU designs may be able to recover from certain types
of L1 instruction cache errors. Rather than panicing
whenever any kind of L1 error is encountered, add an option
to selectively panic on recoverable L1 errors.

Change-Id: Id8beb0e58d41fa5319f4ca76c5f35e2162f8b704
Signed-off-by: default avatarStepan Moskovchenko <stepanm@codeaurora.org>
(cherry picked from commit e1aba3d9b510d34e8309669d811a6f01568858dc)

Signed-off-by: default avatarDhivya Subramanian <dthiru@codeaurora.org>
parent 2739be95
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