msm_fb: display: fix dsi pll setting to reduce phase lock time

Sometimes, it may take up to 8 ms to have dsi PLL phase locked.
Set dsi pll optimal values at PLL_CTRL registers 16 and 17 to
reduce the PLL phase lock time.

CRs-fixed: 468455
Change-Id: I1a6c57e6599052e1864de55cc8d57326b1c367e0
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>