Commit e1faaf22 authored by Tianyi Gou's avatar Tianyi Gou
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msm: clock-8960: Fix SR2 PLL regulator voting for 8064 



8064's SR2 PLL is powered by LVS7. Update the code to reflect
this.

Change-Id: If9b90996f20006b54f40c2807639f6135fadbd76
Signed-off-by: default avatarTianyi Gou <tgou@codeaurora.org>
parent 192db7be
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