msm: clock: Respect voltage constraints for 9615 and 8960 UART dividers

The 16-bit fractional dividers used for these clocks should have
a clock rate no greater than 300MHz applied to their inputs when
running in low voltage mode. Increase the pre-dividers for rates
that previously violated this rule.

Change-Id: Ia7177c8643f8c8051ec9cef6cedcb2a7051d936c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>